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application note surface mounted triacs and thyristors introduction there is an ever growing need in the electronics industry for miniaturisation and cost reduction of the end product. in order to satisfy these requirements, designers are specifying surface mount technology with increasing regularity. at first their attentions were aimed at the low power and small signal components. now their attentions are turning towards the power devices in order to give them total surface mount solutions. the increased miniaturisation is possible because surface mounted power semiconductors occupy less board area than through-hole-mounting devices on heatsinks. cost reduction is possible due to the faster and simpler assembly that result when all components are surface mounted. the availability of a wide range of package sizes permits continuous power dissipations ranging from 0.5 watts to 2 watts on standard printed circuit boards. higher power dissipations are achievable if special heatsinking provisions are made on the pcb. some examples of these include: a grid of solder vias to a pad on the reverse side of the pcb. a pcb-mounted heatsink on one or both sides. an aluminium-cored pcb. fan-assisted cooling. surface mount solutions from philips philips semiconductors has developed a full range of surface mount power packages for its entire range of triacs and thyristors. the assembly materials and technology used are not simply adapted from the pre-existing through-hole-mounting package technology; they are unique to smt. every new smt device is subjected to rigorous testing which originates from stringent automotive requirements. this consists of full reliability testing after three surface mounting operations on printed circuit boards. no failures will be generated. this gives the best assurance of reliable end products. this technical publication will present the surface mount packages and show what thermal performances can be achieved on standard pcbs without special heatsinking arrangements. sot223 sot223 (fig. 1) is the smallest smt power package presented in this publication. the mechanical design has been optimised for maximum ease & versatility of surface mounting, and maximum longterm reliability in the application. it will provide the minimum cost of ownership to the original equipment manufacturer when initial purchase costs, handling costs and final assembly costs are added together. the three legs and the heatsink tab emerge sideways from the edge of the plastic body, where they are formed to bring them into contact with the pcb for soldering to the pads. the centre leg and the larger heatsink tab on the opposite side of the package are internally connected. because the main tab and the three legs emerge from the edge of the plastic package and are formed before they make contact with the pcb, a certain degree of safe movement of the pcb relative to the device is possible as the assembly expands and contracts during soldering and during circuit operation. since the devices diepad is not in direct and intimate contact with the pcb solder pad, differential movement caused by different coefficients of expansion can be accommodated without excessive fatigue stress to the solder joints. the more extreme condition of stresses being transmitted to the die, causing it to crack, is also minimised with this package design. sot223 soldering when soldering most smt power packages, a reflow process must be used. however, for sot223, it is also feasible to use wave soldering if required. wave soldering is possible because the small size of the package minimises the size of the shadow on the downstream side of the solder flow. perhaps more importantly, the exposed nature of the solder connections around the periphery of the package, and their relatively low thermal capacities, mean that
full solder wetting is easily possible with wave soldering. the good visibility of the solder joints allows full inspection for quality after assembly. figures 2 and 3 show the recommended sot223 footprints for reflow soldering and for wave soldering. unit a 1 b p cd e e 1 h e l p qy w v references outline version european projection issue date iec jedec eiaj mm 0.10 0.01 1.8 1.5 0.80 0.60 b 1 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 2.3 e 4.6 7.3 6.7 1.1 0.7 0.95 0.85 0.1 0.1 0.2 dimensions (mm are the original dimensions) sot223 96-11-11 97-02-28 w m b p d b 1 e 1 e a a 1 l p q detail x h e e v m a a b b c y 0 2 4 mm scale a x 13 2 4 plastic surface mounted package; collector pad for good heat transfer; 4 leads sot223 fig. 1. sot223.
handbook, full pagewidth msa443 1.20 (4x) 3.90 5.90 4.80 7.40 4 23 1 3.85 1.20 (3x) 1.30 (3x) 0.30 3.60 3.50 7.00 6.15 7.65 solder lands solder resist occupied area solder paste fig. 2. reflow soldering footprint for sot223. handbook, full pagewidth msa424 8.70 8.90 7.30 1.90 (2x) 6.70 4 123 1.10 8.10 4.30 preferred transport direction during soldering solder lands solder resist occupied area fig. 3. wave soldering footprint for sot223.
sot428 sot428 (also known as to252 and dpak) occupies an area on the pcb which is not much larger than the area required for sot223. indeed, it can be soldered to a universal sot223 / sot428 pad layout. figures 5 and 6 show the pad and relative component sizes. the main pad area of 20mm 2 is the minimum practical pad size for sot428. sot428 has three legs which emerge from one edge of the plastic body. the centre leg is cropped off close to the plastic, so it is not used for electrical connection. the centre leg connection is made from the devices metal backplate to the main pcb pad. the two outer legs are formed to bring them into contact with the pcb pads for soldering. references outline version european projection issue date iec jedec eiaj sot428 97-06-11 0 10 20 mm scale plastic surface mounted package (philips version of d-pak); 2 leads sot428 e b 2 d 1 wa m bc b 1 l 1 l 12 d e 1 h e l 2 note 1. measured from heatsink back to lead. e 1 e a a 2 a a 1 y seating plane a 1 (1) d max. b d 1 max. e max. h e max. w y max. a 2 b 2 b 1 max. c e 1 min. ee 1 l 1 min. l 2 l a max. unit dimensions (mm are the original dimensions) 0.2 0.2 mm 2.38 2.22 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 6.22 5.98 4.81 4.45 2.285 4.57 10.4 9.6 0.5 0.7 0.5 6.73 6.47 4.0 2.95 2.55 fig. 4. sot428.
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5. special locking features are used to lock the epoxy to the metal to improve hermeticity. these features have been carefully optimised to provide good hermeticity without locking the epoxy too rigidly to the diepad, which can result in excess die stress during differential expansion. 6. a bare copper diepad is used for best adhesion of the epoxy to the metal. this promotes good hermeticity. 7. all mating surfaces to be soldered to the pcb pads are tin-lead solder plated for good solderability. 8. the footprint is compatible with jedec and motorola layouts. 9. the coplanarity of leads to seating plane and leads to leads meets stringent industry standards. 10. a fully automatic high volume production line is used which takes in the raw components at its input and delivers assembled, 100% tested, packaged devices at its output. 11. all assembled devices are subjected to an in-line surface mount temperature profile pass to eliminate any remaining possibility, however small, of zero hour defects at the customer. 12. devices are packaged in industry standard blister pack reels for loading onto automatic pick-and- place machines. sot404 sot404 (fig. 9, also known as to263 and d 2 pak) possesses the same size of plastic body as sot78 (to220). the similarity ends there. sot404 is manufactured without a tab since no mounting hole is required. (it is not merely a cropped to220!) the centre lead is cropped close to the plastic, so the centre leg connection is made via the metal backplate. the two outer leads are formed downwards to bring them into contact with the pcb. sot404 soldering as for sot428, it is also not possible to solder sot404 using a wave soldering technique. the even larger body and larger hidden solder area would put this method out of the question. reflow soldering is essential. figure 8 shows the sot404 solder pad dimensions. sot404 design features for surface mountability in designing and manufacturing the sot404 package, similar measures must be taken as for sot428 to ensure a reliable end product. these include: 17.5 11.5 9.0 5.08 3.8 2.0 fig. 8. sot404 solder pad dimensions. 1. a low stress epoxy to minimise bending forces on the mounting base after curing. (minimises die stress.) 2. a thick copper mounting base of 1.4mm (0.055 inches) max thickness to further minimise any tendency to bend. 3. a low stress, high lead content soft diebond solder. (minimises die stress.) 4. accurate dosing and spreading of the die-attach solder prior to diebonding to ensure optimum diebonding over the complete die area every time without unsoldered areas or excess solder. this offers best longterm reliability under thermal cycling and optimum junction-to-mounting base thermal resistance. 5. optimised locking features to balance the conflicting requirements of good hermeticity with sufficient differential movement to avoid die stress fracture. 6. a bare copper comb to ensure good epoxy-to- metal adhesion for best hermeticity. 7. tin-lead solder plating of all exposed copper, including all cropped edges, for optimum solderability. 8. compatibility with the industry standard footprint layout for d 2 pak. 9. coplanarity check on leads to seating plane and leads to leads.
10. a specially designed leadframe to reduce cropping forces as each device is separated from the comb. this avoids die cracking due to shock loading. 11. a surface mount temperature profile pass to eliminate zero hour defects at the customer. 12. devices are packaged in industry standard blister pack reels for loading onto automatic pick-and- place machines. unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d e el p h d q c 2.54 2.60 2.20 15.4 14.8 2.9 2.1 9.65 8.65 1.6 1.2 10.3 9.7 4.5 4.1 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 97-06-16 0 2.5 5 mm scale plastic single-ended package (philips version of d2-pak); 2 leads sot404 e e e b d 1 h d d q l p c a 1 a fig. 9. sot404.
mounting and soldering the sm footprint drawings define the solder land (pad) areas, the solder resist areas and the area occupied by the package. since the solder lands must be completely free of solder resist, the areas without the solder resist are always slighty greater than the solder land areas. the solder resist must cover all areas of the pcb that are not soldered to. this includes extended areas of copper used for heatsinking. the footprints for reflow soldering define the solder paste areas in addition to the areas listed above. solder paste is applied using a metal stencil which must be accurately aligned to within 0.1mm over the pads. a metal squeegee is drawn across the stencil to deposit the paste through the apertures, which must be the same size as the solder paste areas defined on the footprint drawings. with reference to figs. 2 & 3, it can be seen that the optimum pad areas are different for wave soldering and for reflow soldering. when wave soldering, surface mount devices must be held in position by a small measured dose of adhesive. a double wave process is used to ensure better wetting of all joints without solder shadows. wave soldering must be used if there are any through-hole components on the pcb. for reflow soldering, surface mount devices are held in position by the viscosity of the solder paste. when the solder is melted in the reflow oven, the surface tension of the molten solder causes them to self centre on their pads. for self centreing to operate reliably, the pad sizes and configuration are critical. for pcbs which contain a mixture of sm and through-hole components, both soldering methods are sometimes employed in order to ensure optimum soldering of both technologies. a more detailed description of the wave and reflow soldering processes is beyond the scope of this technical publication. for a more detailed description, please see data handbook sc18 entitled smd footprint design and soldering guidelines. thermal resistance - a laboratory investigation. detailed laboratory tests have been conducted on the junction-to-ambient thermal resistance r th j-a of the sot223, sot428 and sot404 sm packages when mounted to different pad sizes on standard fr4 pcb. sufficient time was devoted to this work to ensure repeatability of the results and to give a high level of confidence in their validity. theory it is possible to measure the temperature of a power semiconductor junction by measuring one of its temperature-dependent characteristics. for example, for a mosfet it might be the forward voltage of the anti-parallel diode and for a thyristor it would be the forward voltage drop v t . in order to heat up the device under test, a heating current is passed through it. when measuring its temperature- dependent characteristic, a much lower calibration current is passed for a very short measurement period. for this investigation, thyristors were used because of the relative ease of their measurement and because they were freely available in all the packages of interest. the size of the die within any given package will not affect the final r th j-a result appreciably because any differences in the junction-to-case thermal resistance r th j-c will pale into insignificance compared to the case-to-ambient thermal resistance r th c-a . it is not critical, therefore, which device is used when measuring package r th in free air or when surface mounted to conventional pcbs with relatively high thermal resistances to ambient. fr4 fibreglass pcb with 35 m m copper (1oz/square foot) was used because it is an industry standard to which everyone can relate. it is the pcb type which is always quoted in power semiconductor manufacturers data sheets. it has become a reference standard by default. despite this standard status, many industries cannot justify its use because of its cost. the home appliance industry prefers to use a lower cost alternative, one example of which is cem3. this is a resin and paper-based material with fibre on both sides. fortunately, the thermal performance of the cheaper alternatives is sufficiently close to that of fr4 in many cases to make the results of this investigation valid for those also. equipment the test pcbs had pad sizes which varied upwards from the minimum recommended for the package. consistent pad width / height ratios were maintained. the pad was always positioned centrally on the test board to assure consistent heatsinking to the bulk of
the pcb. sot223 and sot428 used the same pad layouts, while sot404 had its own pcbs. figure 10 shows the second smallest and largest pad size test boards for sot223 / sot428, and fig. 11 shows the smallest and largest pad size test boards for sot404. note that these test boards are not shown full scale. fig. 10. sot223 / sot428 test pcb layout, small and large pad areas. fig. 11. sot404 test pcb layout, small and large pad areas. separate power and measurement connections were taken via an edge connector to the device. the pcbs were standard fibreglass fr4 with 35 m m copper which had been very lightly tinned by electrochemical deposition. (thermal resistance will not be reduced by a thick layer of roller tinning!) the
pcbs were made relatively large at 100mm x 100mm to ensure that r th is controlled by pad area and not by pcb area. thyristors were tested using a purpose built thermal resistance test gear. (thyristors were tested in preference to triacs because they only require one measurement for each power setting, whereas triacs need measuring in both directions with the average power being calculated from the results.) the most important fact to remember when conducting the tests was that they take a lot of time. it was essential to ensure that thermal equilibrium and stability had been reached before readings were taken at elevated device temperature. rushing the tests would give incorrect results and improbable graphs. this was learned from experience. results the resolution and accuracy of the final r th j-a results were maximised by generating high values of d t j , hence large measured d v. the results tables show r th j-a (k/w) versus power dissipation and pad area. the power levels highlighted by an asterisk indicate a suggested power dissipation limit for the package when soldered to the minimum pad area on fr4 pcb. (in the case of the sot223 package, the smallest pad area used was 20mm 2 . this area is fully occupied by the sot428 package. the minimum for sot223 is actually 5.7mm 2 . therefore the 1w power dissipation achieved in these experiments will be higher than that achievable with a 5.7mm 2 pad. 0.5w is likely to be a practical maximum power dissipation for sot223 on a 5.7mm 2 pad.) the results graphs show r th j-a versus pad area and d t j versus pad area. for any given package, higher power dissipation leads to higher d t j which leads to lower r th j-a . this is because a larger temperature difference results in more efficient radiation to ambient. sot223 area (mm 2 ) 0.5w 1.0w* 1.5w 20 110 110 - 49 99 98 - 81 91 90 90 144 88 87 86 256 78 79 78 484 73 74 73 900 68 69 69
sot223 rth j-a vs pcb pad area. 100 x 100 mm fr4 pcb positioned vertically in still air. 65 70 75 80 85 90 95 100 105 110 0 200 400 600 800 1000 pad area (sq mm) rth j-a (k/w) 0.5w 1w 1.5w sot223 tj rise vs pcb pad area. 100 x 100mm fr4 pcb positioned vertically in still air. 0 20 40 60 80 100 120 140 0 200 400 600 800 1000 pad area (sq mm) delta tj (deg c) 0.5w 1w 1.5w
sot428 area (mm 2 ) 0.5w 1.0w* 1.5w* 2.0w 2.5w 3.0w 209085---- 49 77 75 73 72 - - 81 71 69 66 65 - - 144 64 62 60 59 58 - 256 58 56 54 53 52 - 484 54 50 48 47 46 45 900 46 45 43 43 42 41 sot428 rth j-a vs pcb pad area. 100 x 100 mm fr4 pcb positioned vertically in still air. 40 50 60 70 80 90 100 0 200 400 600 800 1000 pad area (sq mm) rth j-a (k/w) 0.5w 1w 1.5w 2w 2.5w 3w
sot428 tj rise vs pcb pad area. 100 x 100mm fr4 pcb positioned vertically in still air. 0 20 40 60 80 100 120 140 160 0 200 400 600 800 1000 pad area (sq mm) delta tj (deg c) 0.5w 1w 1.5w 2w 2.5w 3w sot404 area (mm 2 ) 1.0w 2.0w* 3.0w 103.5 60 55 - 192 52 47 - 300 47 43 41 475 41 39 37 825 39 36 34 1200 36 34 32
sot404 rth j-a vs pcb pad area. 100 x 100mm fr4 pcb positioned vertically in still air. 30 35 40 45 50 55 60 0 200 400 600 800 1000 1200 pad area (sq mm) rth j-a (k/w) 1w 2w 3w sot404 tj vs pcb pad area. 100 x 100mm fr4 pcb positioned vertically in still air. 0 20 40 60 80 100 120 140 0 200 400 600 800 1000 1200 pad area (sq mm) delta tj (deg c) 1w 2w 3w
conclusions the maximum practical power dissipations are summarised below for stagnant ambient conditions at 25 c. these are for standard fr4 pcb or similar without special heatsinking provisions. the 35 m m copper had been lightly tinned by electrochemical deposition. sot223 and sot428 can be soldered to common pad layouts. 20mm 2 was the absolute minimum pad area for soldering sot428. a reasonable power dissipation for sot428 on 20mm 2 fell somewhere between 1.0w and 1.5w. the minimum pad quoted in data for sot223 is 5.7mm 2 . 0.5w is a more realistic maximum power dissipation for sot223 on its minimum pad. package pmax (w) pad area (mm 2 ) d t j ( o c) r th j-a (k/w) r th j-a (k/w) (experimental) (quoted in data) sot223 1.0 20 650 97 74 99 72 156 (5.7mm 2 pad) 70 (648mm 2 pad) sot428 1.0<1.5 20 106 73 75 sot404 2.0 104 108 55 55 naked dice all philips thyristors and triacs can be supplied as naked dice if required. please contact your local sales office for details.

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